1. Field of the Invention
The present invention relates to a boosting circuit, and more specifically, to a boosting circuit for outputting a boosted voltage higher than a power supply voltage from a boost terminal.
2. Description of the Related Art
At present, in a semiconductor device, there may be employed a boosting circuit for outputting a boosted voltage higher than a power supply voltage from a boost terminal. For example, in a non-volatile semiconductor device, the boosting circuit is installed because the boosted voltage is used at the time of writing/erasing into/from a memory cell transistor.
A known example of such boosting circuit is a threshold offset type boosting circuit, which is driven in response to four-phase clock signals to achieve high boost efficiency. This boosting circuit generally includes a plurality of booster cells each of which boosts an input voltage V1 and outputs the boosted input voltage. The boosting circuit includes, for example, four booster cells. Charges are transferred from a boosting capacitor included in the first-stage booster cell into a boosting capacitor included in the second-stage booster cell. Similarly, the charges are transferred from the second-stage booster cell to a third-stage booster cell, and further similarly, the charges are transferred from the third-stage booster cell to a fourth-stage booster cell. As a result, the boosted voltage appears at the boost terminal of the boosting circuit.
Now, a booster cell installed in a conventional boosting circuit is described.
FIG. 6 is a diagram illustrating the conventional booster cell.
If a voltage of a clock terminal CLKS changes to a power supply voltage V2 from a ground voltage, due to the coupling of a capacitor C12, a voltage of a node Vz sufficiently increases to as high as a total voltage (V1+V2) of an input voltage V1 of an input terminal VIN and the power supply voltage V2. Accordingly, a charge transfer transistor M11 is turned ON so that an output voltage of an output terminal VOUT may become the input voltage V1 of the input terminal VIN. Then, charges are stored into a boosting capacitor C11 with the input voltage V1 of the input terminal VIN. On this occasion, because the output terminal VOUT and the input terminal VIN have the equal voltage, a gate voltage and a source voltage of a transistor M12 are equal to each other, and a gate-source voltage of the transistor M12 is lower than its threshold voltage. Accordingly, the transistor M12 is turned OFF.
On the other hand, if a voltage of a clock terminal CLKM changes to the power supply voltage V2 from the ground voltage, due to the coupling of the boosting capacitor C11, the input voltage V1 of the input terminal VIN transferred into the boosting capacitor C11 is boosted at the output terminal VOUT to the total voltage (V1+V2) of the input voltage V1 of the input terminal VIN and the power supply voltage V2. On this occasion, because the output voltage of the output terminal VOUT has increased sufficiently, the transistor M12 is turned ON. Then, the voltage of the node Vz becomes the input voltage V1 of the input terminal VIN. Thus, because the node Vz and the input terminal VIN have the equal voltage, a gate voltage and a source voltage of the charge transfer transistor M11 are equal to each other, and a gate-source voltage of the charge transfer transistor M11 is lower than its threshold voltage. Accordingly, the charge transfer transistor M11 is turned OFF.
On this occasion, a voltage of a reset terminal R is controlled to a predetermined voltage higher than the power supply voltage V2. In addition, a terminal VCC is applied with the power supply voltage V2. In other words, a gate voltage of a transistor M13 becomes the above-mentioned predetermined voltage, and a source voltage thereof becomes the power supply voltage V2. Accordingly, a gate-source voltage of the transistor M13 is higher than its threshold voltage, and hence the transistor M13 is turned ON. The node Vz is discharged from the total voltage (V1+V2) of the input voltage V1 of the input terminal VIN and the power supply voltage V2 to a total voltage of the power supply voltage V2 and a threshold voltage of a transistor M14 (see, for example, JP 2003-250263 A).
In the conventional technology, the predetermined voltage higher than the power supply voltage V2 is used for the reset terminal R at the time of resetting the boosting circuit. Therefore, an additional boosting circuit is required for the reset, which arises a problem that a circuit scale of the boosting circuit is increased correspondingly to the additional boosting circuit.